Netrasemi

Netrasemi designs and owns its own hardware IP blocks rather than licensing third-party cores, per CEO Jyothis Indirabhai.

Chips run advanced AI analytics locally on the device, removing the need to send data to a server or the cloud — lowering latency and improving privacy.

Rather than chasing raw AI TOPS benchmarks, Netrasemi optimizes for application-level performance per watt via a multi-kernel (NPU+CV+ISP+video codec) hardware mix tuned to each use case.

On-device analytics for ANPR, intrusion, crowd density and behavior detection in smart cameras, without sending video to the cloud.

Low-latency on-device perception for SLAM, obstacle avoidance, path planning and visual navigation in robotics and drones.

On-device perception for driver/occupant monitoring, surround view, parking assist and telematics in vehicles.

On-device AI for driver monitoring, telematics and route optimization for logistics/fleet operators.

In-store AI analytics for foot traffic, shelf monitoring and checkout-free experiences.

High-accuracy inspection/QA for factories and logistics — defect detection, OCR, pose estimation, multi-camera fusion.

Netrasemi runs paid/co-development style engagements with OEM customers — sharing chip designs and working jointly through evaluation to production.

Chip designs are shared directly with select OEMs for joint R&D rather than through distributors; the company solicits partners via "Interested to Partner / Contact Us" on its own site.

Tailored AI-chip architecture design work optimized for edge performance across application segments.

For each customer use-case Netrasemi architects the full vision pipeline — model selection/quantization, memory & throughput budgeting and reference-board mapping — using its own SDKs/toolchains, ahead of development, testing and pilot deployment.

An energy-efficient, graph-like streaming (configurable pipelining) architecture for vector data between acceleration kernels with minimal CPU involvement — lets many parallel AI-model pipelines run on one cost-effective SoC.

Neural processor (NPU), vision cores (VPU), image signal processor (ISP) and crypto-engines developed in-house and integrated into the A2000 SoC.

A Universal Chiplet Interconnect Express (UCIe)-based die-to-die interconnect for multi-die extension of Netrasemi's Domain Specific Architecture, enabling higher-TOPS multi-chiplet configurations.

A2000 and R1000 are fabricated at TSMC's 12nm advanced process node in Taiwan; volume/commercial production is also planned there for 2027.

Netrasemi was one of the first four startups selected for government design-support funding under India's semiconductor Design Linked Incentive scheme.

The R1000 AI/ML microcontroller was co-developed with CET under the government's Chip-to-Startup (C2S) program — an academic-industry silicon design collaboration.