India Semiconductor Mission: Semicon 2.0 Explained

Key takeaways

• India Semiconductor Mission 2.0 was formally notified on 31 August 2026 with a ₹1,27,500 crore outlay, turning July’s Cabinet approval into an operating framework.
• The scheme spans six pillars and 10 support categories: design, machines and materials, fabs, advanced packaging, research and development, and talent.
• Reported support includes 40% of eligible capital expenditure for silicon fabs, 35% for several compound-semiconductor and advanced-packaging projects, and design seed funding capped at ₹15 crore.
• The government says 85,000 semiconductor engineers have already been trained and has set a new target of one lakh more; the new target is not an existing workforce count.
• The decisive test is disbursement and production. PRS found that the first Semicon India scheme used only 23% of its budget in 2023-24 and 9% in 2024-25 because incentives are released after milestones are met.

The India Semiconductor Mission has moved into its second phase. The government notified all six pillars of Semicon 2.0 on 31 August, creating detailed routes for public support across chip design, fabrication, equipment, materials, packaging, research and workforce development under a ₹1,27,500 crore programme.

The new development is the framework, not the headline budget alone. The Union Cabinet approved the outlay on 15 July, but the notification explains who may qualify, which technologies receive support and how long projects can run. Everyone else is reporting ₹1.27 lakh crore; we are explaining the conversion chain from an approved scheme to applications, milestones, disbursements and commercially useful production.

What changed when India Semiconductor Mission 2.0 was notified?

Cabinet approval established the government’s intent and spending ceiling. The 31 August notification made the second India Semiconductor Mission phase actionable by setting out six pillars and 10 categories of support. The India Semiconductor Mission, or ISM, will serve as the nodal agency that invites applications, conducts technical and financial appraisals, and recommends projects to the Ministry of Electronics and Information Technology.

Business Standard reported that support can run for up to six years, while the duration of each project will be decided case by case. That matters because a design startup, an advanced-packaging line and a large silicon fabrication plant have very different capital needs and construction timelines.

The framework is broader than a subsidy for one giant factory. It tries to connect intellectual property, machinery, chemicals, gases, wafer fabrication, assembly and testing, research, and trained workers. A domestic fab remains important, but it cannot operate competitively without a reliable network of suppliers and customers.

India Semiconductor Mission 2.0 is a full-value-chain industrial policy, not simply a fab subsidy. Its success will be measured by how many supported designs, materials, tools, wafers and packaged chips reach repeat commercial production—not by the ₹1,27,500 crore ceiling alone.

How the ₹1,27,500 crore support is structured

The outlay is a programme ceiling, not cash paid upfront. Eligible projects must apply, pass technical and financial appraisal, commit their own capital and meet milestones. Different technologies receive different percentages and thresholds because their economics and strategic value differ.

Business Standard reported 40% fiscal support for eligible capital expenditure on silicon semiconductor wafer fabs. It reported 35% support for compound semiconductors, photonics, sensors and discrete-semiconductor fabs, with a ₹500 crore minimum investment threshold for that group. Moneycontrol separately reported 35% support for advanced packaging technologies such as 2.5D and 3D packaging, wafer-level chip-scale packaging and heterogeneous integration, while legacy packaging receives a lower 25% rate.

Design support follows another model. Eligible startups and micro, small and medium enterprises can receive seed funding of up to ₹15 crore. Milestone-linked advance seed funding can cover up to 50% of project cost but remains subject to the same ₹15 crore ceiling. Larger design companies may use royalty financing or equity co-investment instead.

Semicon 2.0 route	Reported public support	What applicants still must prove
Silicon wafer fabs	40% of eligible capital expenditure	Technology, financing, scale and execution capability
Compound, photonics, sensor and discrete fabs	35%; reported minimum investment ₹500 crore	Production-grade technology and a credible market
Advanced packaging	35% of eligible capital expenditure	Advanced process capability and customer qualification
Legacy packaging	25% of eligible capital expenditure	Cost competitiveness and dependable volumes
Startup/MSME design projects	Seed support up to ₹15 crore; up to 50% of project cost	Milestones, usable IP and a deployment path

These percentages should not be read as guaranteed cheques. Eligible capital expenditure must be verified, and public money is normally released alongside or after private spending and project progress. The India Semiconductor Mission therefore shares part of the risk without removing the applicant’s obligation to build and operate.

Why India Semiconductor Mission 2.0 reaches beyond fabs

Semiconductor manufacturing depends on a long chain. Chip designers create the architecture and electronic files. Equipment makers provide lithography, deposition, etching and inspection tools. Materials companies supply wafers, specialty gases and chemicals. Fabs manufacture circuits, while ATMP and OSAT companies assemble, package and test them before electronics companies place the chips into products.

A country may perform one step without controlling the whole chain. India already has a large chip-design workforce, yet much of the physical manufacturing, equipment and materials base sits abroad. Semicon 2.0 attempts to close those gaps rather than treating the first fab as the finish line.

This approach also creates openings outside conventional silicon. Photonics, sensors, power electronics, compound semiconductors and advanced packaging serve electric vehicles, telecom networks, satellites, factories and AI systems. Lapaas Voice’s report on the Olee.space photonics programme shows how specialised hardware development can connect research, strategic demand and commercial manufacturing.

What Semicon 1.0 achieved—and what it did not

The first Semicon India programme was approved in 2021 with a ₹76,000 crore outlay. The government’s July 2026 progress statement said 12 manufacturing units had been approved with cumulative proposed investment above ₹1.64 lakh crore. These included one silicon fab, one silicon-carbide fab, an integrated gallium-nitride micro-LED display fab and nine packaging units.

The same statement said Micron, Kaynes and CG Semi had started commercial production, with another unit expected to start during 2026. It also counted 24 design projects approved for financial support and 105 startups or MSMEs given access to industry-standard electronic design automation tools.

Those are meaningful pipeline indicators, but approvals and proposed investment are not output. A more demanding scorecard asks how much public support was disbursed, how much production passed customer qualification, what share of equipment and materials was sourced locally, and whether products won repeat orders.

PRS Legislative Research identified the central execution problem. It reported that the first scheme used 23% of allocated funds in 2023-24 and 9% in 2024-25; utilisation was estimated at 61% in 2025-26. PRS attributed underuse to the scheme structure because firms receive incentives only after meeting targets. That can protect taxpayers from paying for stalled projects, but it can also reveal delays in construction, qualification or claims.

The talent target needs careful wording

The original draft said Semicon 2.0 “aims to add one lakh chip engineers” without distinguishing past achievement from the new goal. The official 31 August Press Information Bureau release says India achieved its earlier target of developing 85,000 semiconductor engineers in four years, against a 10-year timeline, and has now set a target of developing one lakh more.

The Cabinet’s July note provided a different but compatible snapshot: 315 universities were training students with modern electronic design automation tools and about 68,000 students had already been trained at that point. The later 85,000 figure was announced by Electronics and IT Minister Ashwini Vaishnaw after the notifications were issued.

Training numbers still require context. Designing a chip in a university programme is different from running a high-volume fab, building a clean room, maintaining precision equipment or qualifying an advanced package for an automotive customer. The talent pillar therefore includes deeper design education as well as fab construction, clean-room and ecosystem training with industry participation.

What could make India Semiconductor Mission 2.0 work?

First, India needs anchor customers. A plant can receive a subsidy and still struggle if device makers do not qualify its output or commit long-term orders. Automotive, telecom, industrial, defence and consumer-electronics buyers must be involved before capacity is built, not approached only after commissioning.

Second, suppliers need predictable demand. Chemicals, gases, wafers, equipment servicing and testing laboratories will not localise on the strength of one plant. A portfolio of fabs and packaging units can create the volume that justifies these investments.

Third, central and state support must fit together. Semiconductor plants require reliable power, treated water, logistics, land and fast permits. State incentives can improve project economics, but fragmented approvals or unrealistic infrastructure promises can delay the national programme.

Fourth, the government must publish a transparent funnel: applications received, projects approved, private capital committed, incentives disbursed, milestones completed, production started and customers qualified. That would separate industrial progress from headline announcements and make the India Semiconductor Mission easier to evaluate.

The same discipline applies across advanced manufacturing. Lapaas Voice’s coverage of the Mahindra Aerostructures Airbus contract shows why certification and repeat orders matter, while its analysis of private equity investment in India explains how committed capital differs from operating results.

What investors, founders and students should watch next

Founders should watch the application windows, intellectual-property terms, milestone definitions and the difference between grant, royalty and equity support. A high reimbursement percentage matters less if a young company cannot finance its share of spending before a milestone payment arrives.

Manufacturers should watch how eligible capital expenditure is defined and whether specialised tools, imported equipment, infrastructure and technology licensing qualify. They should also track project-specific timelines because support may extend up to six years but will not be identical for every category.

Students should look beyond the headline promise of one lakh additional engineers. The strongest opportunities are likely to be in verifiable skills: analogue and digital design, verification, embedded systems, process engineering, packaging, reliability, equipment maintenance, clean-room operations and materials science.

The next national checkpoint is not another announcement. It is the first public set of applications and approvals under the notified rules, followed by evidence that private capital and customer orders are moving with public support.

FAQs

What is India Semiconductor Mission 2.0?

India Semiconductor Mission 2.0 is the second phase of India’s semiconductor industrial policy. It offers support across six pillars: design, machines and materials, fabs, ATMP/OSAT packaging, research and development, and talent.

How large is the Semicon 2.0 outlay?

The Union Cabinet approved a total outlay of ₹1,27,500 crore. This is a programme ceiling distributed across eligible projects and milestones, not an upfront payment to one company.

When was Semicon 2.0 notified?

The Cabinet approved the programme on 15 July 2026. The government issued notifications for all six pillars on 31 August 2026, making the detailed framework the fresh news event.

Does Semicon 2.0 promise one lakh new engineering jobs?

No. The government says 85,000 semiconductor engineers were already trained and has set a new target to develop one lakh more. A training target is not the same as a guarantee of one lakh jobs.

Sources: the Press Information Bureau’s 31 August notification update; the Prime Minister’s Office summary of the Semicon 2.0 Cabinet decision and six pillars; PRS Legislative Research’s 2026-27 MeitY spending analysis; Business Standard’s notification analysis; and Moneycontrol’s incentive breakdown.