Taiwan Semiconductor Manufacturing Co. (TSMC) has completed development and validation of its next-generation A16 semiconductor process, a 1.6nm-class technology designed primarily for artificial intelligence and high-performance computing (HPC) chips. Taiwanese media reports say the company is preparing to begin mass production in the fourth quarter of 2026, marking the next major step in its advanced-node roadmap after 2nm.
The A16 process is significant because it introduces TSMC’s Super Power Rail (SPR), a backside power-delivery technology that moves power connections to the back of the wafer. TSMC says the approach frees space on the front side for signal routing and can deliver an 8% to 10% speed improvement, 15% to 20% lower power consumption at the same performance, and up to 1.10 times the chip density compared with its N2P process.
TSMC Completes Development Of 1.6nm A16 Process
A16 represents TSMC’s move into what the industry increasingly describes as the angstrom-class era of semiconductor manufacturing. The “1.6nm” designation is a process-generation label rather than a direct measurement of a single transistor dimension, but it represents a technology generation beyond TSMC’s 2nm family.
The company has previously said A16 would be production-ready in the second half of 2026. Recent Taiwanese media reports now point specifically to the fourth quarter for mass production, making the latest timeline consistent with TSMC’s earlier guidance.
TSMC A16 At A Glance
| Metric | TSMC A16 |
|---|---|
| Process class | 1.6nm |
| Technology generation | Angstrom-class |
| Production target | Q4 2026 |
| Power technology | Super Power Rail (SPR) |
| Speed improvement vs N2P | 8–10% |
| Power reduction at same speed | 15–20% |
| Maximum chip-density improvement | Up to 1.10x |
| Primary target | AI and HPC |
| Transistor architecture | Nanosheet |
| Production readiness | 2H 2026 |
TSMC’s own technical material describes A16 as combining nanosheet transistors with its backside power-rail solution. The company specifically positions the process for HPC products that have complex signal routes and dense power-delivery networks.
Super Power Rail Is The Key Technology
The most important change in A16 is not simply the smaller process label. It is the introduction of Super Power Rail, which moves the power-delivery network to the backside of the wafer.
In conventional chip designs, power and signal wiring compete for space on the front side of the chip. As transistor density and computing requirements increase, those routing constraints become increasingly difficult to manage.
TSMC’s backside approach separates the power network from much of the front-side signal routing. This creates additional room for data connections and can reduce voltage losses across the chip.
How TSMC’s Backside Power Approach Works
| Traditional Approach | A16 With SPR |
|---|---|
| Power delivery on front side | Power delivery moved to backside |
| Power and signal routing share front-side resources | More front-side resources available for signals |
| Greater routing congestion | Reduced signal-routing bottlenecks |
| Conventional power delivery | Super Power Rail |
| Higher potential IR drop | Lower IR drop |
| Limited routing flexibility at advanced nodes | Greater routing flexibility |
TSMC says SPR significantly reduces IR drop, which refers to voltage loss caused by electrical resistance. Better power delivery becomes increasingly important as high-performance chips require large amounts of power within tightly packed areas.
A16 Targets AI And High-Performance Computing
TSMC is positioning A16 primarily for high-performance computing rather than treating it simply as the next smartphone processor node.
AI accelerators and other HPC chips can contain extremely dense computing logic and complex networks connecting different parts of the processor. These designs can place substantial demands on both power delivery and signal routing.
That makes the benefits of backside power particularly relevant.
A16’s Reported Advantages Over N2P
| Performance Area | A16 vs N2P |
|---|---|
| Speed at same Vdd | +8% to +10% |
| Power at same performance | -15% to -20% |
| Chip density | Up to 1.10x |
| Target workload | Complex HPC designs |
| Power architecture | Backside Super Power Rail |
The figures are TSMC’s process-level specifications, rather than guarantees for every finished chip. Actual improvements will depend on chip architecture, design choices, workloads and how customers use the additional performance and power headroom.
Why Power Efficiency Matters For AI Chips
AI accelerators are becoming increasingly power hungry as model sizes and computing workloads grow. Data-centre operators must account not only for the cost of the processors themselves but also for electricity, cooling and the infrastructure needed to run them.
A 15% to 20% reduction in power consumption at equivalent performance could therefore have substantial implications when multiplied across large AI accelerator clusters.
For chip designers, the objective is no longer simply to put more transistors into a smaller area. They also need to move data efficiently, deliver power reliably and control heat.
A16’s architecture addresses several of those challenges simultaneously.
Why Advanced AI Chips Need Better Power Delivery
| Challenge | Importance |
|---|---|
| Higher transistor density | More computing in less physical space |
| Increased power demand | AI workloads require substantial energy |
| Signal congestion | More data must move between computing blocks |
| Heat generation | Higher power density increases cooling requirements |
| IR drop | Voltage losses can affect chip performance |
| Data-centre efficiency | Lower power can reduce operating costs |
This is why TSMC describes A16 as particularly suitable for HPC products with complex signal routing and dense power-delivery requirements.
TSMC’s 2nm Family Is Already In Production
A16 follows TSMC’s N2 technology, which entered high-volume production in the fourth quarter of 2025.
TSMC said N2 began volume manufacturing at its Hsinchu and Kaohsiung facilities and was seeing strong demand from both smartphone and HPC/AI applications. N2P, an enhanced version of the 2nm family, is scheduled for volume production in the second half of 2026.
TSMC Advanced-Node Roadmap
| Process | Technology | Production Timeline |
|---|---|---|
| N2 | 2nm nanosheet | Volume production began Q4 2025 |
| N2P | Enhanced 2nm | 2H 2026 |
| A16 | 1.6nm-class + SPR | Q4 2026 target |
| A14 | 1.4nm-class | 2028 target |
| A13 | 1.3nm-class | 2029 target |
| A12 | 1.2nm-class | 2029 target |
TSMC has described N2, N2P, A16 and derivatives as part of a broader family intended to support the company’s advanced-node leadership for an extended period.
A16 Could Strengthen TSMC’s AI Chip Position
The timing of A16 is important because demand for advanced AI processors continues to drive semiconductor investment.
Leading AI chip designers increasingly require manufacturing processes that can deliver high performance without allowing power consumption to grow at the same rate. Foundries capable of meeting those requirements can become strategically important to the entire AI hardware ecosystem.
A16’s combination of nanosheet transistors and backside power delivery gives TSMC another tool for addressing those requirements.
The process could be particularly attractive for custom AI accelerators and data-centre processors where power efficiency and high-density computing are more important than maximizing compatibility with older chip designs.
TSMC Maintains A Technology Lead Over Samsung
The A16 development also matters in the competitive foundry market.
Samsung and Intel are both pursuing advanced sub-2nm technologies. Samsung previously announced plans for a 1.4nm process, but recent reporting says the company has pushed its mass-production target for that technology to 2029. TSMC, meanwhile, is targeting A14 production in 2028.
Advanced-Node Competition
| Company | Advanced Process | Reported Production Target |
|---|---|---|
| TSMC | A16, 1.6nm-class | Q4 2026 |
| TSMC | A14, 1.4nm-class | 2028 |
| Samsung | 1.4nm-class | 2029, according to recent reports |
| Intel | 18A | Advanced production ramp underway |
The comparison is not based solely on the number attached to each process. Manufacturing yields, customer adoption, wafer capacity, packaging capabilities and power-performance characteristics all determine whether a node succeeds commercially.
For TSMC, reaching volume production on schedule could nevertheless reinforce its position as the leading contract chip manufacturer.
Advanced Packaging Is Also Becoming Critical
The development of advanced process nodes is only one part of the AI-chip supply chain.
As AI processors become larger and more complex, advanced packaging technologies are increasingly important for connecting multiple dies and high-bandwidth memory. TSMC has been investing heavily in technologies such as chip-on-wafer-on-substrate, or CoWoS, to support AI demand.
Reports have also pointed to capacity constraints in advanced packaging, illustrating that producing leading-edge wafers is not enough. Chipmakers need sufficient packaging capacity to turn those wafers into complete AI processors.
This creates another potential bottleneck as A16 moves toward mass production.
TSMC Has Approved Major Advanced-Technology Investment
TSMC’s investment plans also demonstrate the scale of the infrastructure required to support new process generations.
Recent reporting said the company’s board approved approximately $29.44 billion in capital expenditure for advanced processes and packaging. Such investments cover the equipment and facilities needed to increase production capacity and support increasingly sophisticated manufacturing technologies.
A16’s Commercial Significance
| Factor | Potential Impact |
|---|---|
| 1.6nm-class process | Higher transistor density |
| Backside power delivery | Better power and routing efficiency |
| AI/HPC focus | Exposure to fast-growing compute demand |
| Q4 2026 production | Earlier commercialization |
| N2P comparison | Clear performance and efficiency benchmark |
| Advanced packaging | Critical for complete AI systems |
| Large capital investment | Supports manufacturing scale |
The combination of process development and packaging investment indicates that TSMC is preparing for continued demand from increasingly complex AI and HPC processors.
The Bigger Picture
TSMC’s A16 process represents a significant transition in semiconductor manufacturing because it combines further transistor scaling with a major change in how power is delivered to the chip. The company’s Super Power Rail architecture is designed to free front-side space for signal routing while improving power-delivery efficiency, addressing challenges that become more severe as AI and HPC processors grow more complex.
The planned Q4 2026 mass-production timeline also places TSMC at an important point in the global foundry race. If the company executes the ramp successfully, A16 could strengthen its position with AI and HPC customers while laying the groundwork for the 1.4nm A14 generation. The next challenge will be scaling production yields and packaging capacity quickly enough to meet demand.
Looking Ahead
The immediate milestone for TSMC is the transition from completed A16 development and validation to volume manufacturing in the fourth quarter. The company has already publicly targeted production readiness in the second half of 2026, while recent reports provide the more specific Q4 timeline. The performance gains claimed by TSMC will ultimately need to translate into real customer products and large-scale manufacturing.
For the semiconductor industry, A16 could mark an important step in the shift toward backside power delivery as advanced chips become increasingly constrained by power and signal-routing requirements. If TSMC can combine its process advantages with sufficient capacity and advanced packaging, the technology could become particularly important for the next generation of AI accelerators and high-performance computing systems.
Get the day’s top stories in your inbox
One concise email. No spam, unsubscribe anytime.
