Semicon 2.0 will target at least 200 startups and companies working on chip design in India, Electronics and IT Minister Ashwini Vaishnaw said at the opening of SEMICON India 2026 on 17 September. The number is a participation ambition inside the already approved ₹1,27,500 crore programme—not a promise that 200 firms will automatically receive funding.
- The design pillar aims to expand participation from more than 105 companies and startups in the first phase to at least 200.
- The programme covers six connected pillars, from design and materials to fabs, packaging, research and talent.
- Execution quality will depend on commercial tape-outs, customers and domestic tooling—not only approved projects or training counts.
The disclosure adds an operating target to a scheme the Union Cabinet approved in July. The government’s Press Information Bureau says Semicon 2.0 is intended to span the full value chain rather than concentrate mainly on fabrication and assembly incentives. The practical shift is from attracting plants to creating a system in which designs, equipment, materials, research and trained workers can reinforce one another.
What the Semicon 2.0 design target changes
Under the first phase, more than 105 startups attempted chip design, according to the minister’s remarks reported by Business Standard. About 20 attracted roughly ₹800 crore in venture funding. The new target of at least 200 companies therefore seeks a much wider top of funnel, but participation is not the same as a commercially successful semiconductor company.
Chip design businesses face unusually long development cycles. A team may need licensed electronic-design-automation tools, access to reusable intellectual property, an affordable route to tape-out, packaging and testing partners, and a customer prepared to qualify the final device. A programme can lower several of those barriers, but demand and repeat orders determine whether a design becomes a durable business.
| Fact | Verified detail |
|---|---|
| New design target | At least 200 startups and companies |
| Programme outlay | ₹1,27,500 crore |
| Strategic pillars | Six |
| Prior design participants | More than 105 |
| Prior projects funded | About 20 |
| Engineer training progress | 70,000 trained against an 85,000 target |
The six-pillar structure matters because weak links can cancel gains elsewhere. A design incentive is less useful if prototypes wait for overseas packaging. A new fab will not necessarily create defensible domestic intellectual property if its product mix and equipment remain imported. Applied research can struggle to leave the laboratory without shared pilot lines, testing capacity and buyers willing to validate locally designed chips.
Semicon 2.0 is broader than fab subsidies
The government’s 17 September background note lists design, machines and materials, new fabrication units, advanced packaging, applied research and talent as the six pillars. It says Semicon 1.0 approved 12 manufacturing units representing more than ₹1.64 lakh crore of cumulative investment and that five units have begun commercial production.
Those figures describe approved and operating capacity, not domestic value addition by themselves. The next test is how much engineering, equipment maintenance, specialty chemicals, process knowledge and chip intellectual property India retains. That is why the machines-and-materials pillar may be as consequential as another headline fab approval.
The talent pillar is also moving from design engineers toward factory skills. Business Standard reported that 70,000 design engineers had already been trained against an earlier ten-year target of 85,000. The minister added a new ambition to develop one lakh technicians, cleanroom personnel and factory-floor workers for upcoming facilities.
Training numbers should be read alongside placement, tool access and project outcomes. Giving universities access to modern EDA tools can broaden the talent base, while shared tape-out facilities can turn classroom designs into testable silicon. But the programme will need transparent evidence on completed tape-outs, first customer wins and the share of designs reaching volume production.
Where startups fit in India’s chip stack
Startups are most likely to compete where capital needs are lower than building a leading-edge fab. That includes specialized processors, mixed-signal chips, power electronics, sensors, chiplets, verification tools and design intellectual property. India’s established base of design engineers can help, but young companies still need dependable access to fabrication, packaging and certification.
The ecosystem already includes adjacent moves such as the HCLTech semiconductor lab in Bengaluru and the Hirata–ATS wafer-automation partnership. Funding events such as VerifAIX’s chip-verification seed round show how software and validation layers can grow alongside physical manufacturing.
A useful Semicon 2.0 scorecard would separate applications, approvals and commercial outcomes. It should disclose how many teams complete a design, how many achieve tape-out, how many receive working samples, how many secure customers and how many generate recurring revenue. Without that progression, a large participation target could overstate the depth of the industry.
What businesses should watch next
The immediate details to watch are pillar-specific guidelines, eligible costs, application schedules and the treatment of venture-backed startups versus larger design houses. Industry will also look for rules on domestic intellectual property, matching private capital, procurement support and access to shared infrastructure.
Semicon 2.0’s real economic consequence will be measured by coordination. If design support, equipment capability, research, talent and manufacturing arrive on different timelines, firms will continue to bridge gaps abroad. If the pillars move together, India could shorten the route from an engineer’s design to qualified, packaged silicon sold into real products.
Private capital will be another useful test. Government incentives can absorb some development risk, but professional investors will still look for defensible intellectual property, credible founders, clear end markets and routes to manufacturing. The first phase’s roughly ₹800 crore of venture funding across about 20 companies gives the new programme a baseline. Progress would mean more companies raising follow-on capital after technical milestones, rather than surviving only while grants remain available.
Procurement can close the loop. Automotive, telecom, energy, defence and industrial buyers often require long qualification cycles, making early reference customers unusually valuable. Transparent public procurement pathways could help Indian designs prove reliability, but they must preserve performance and safety standards. The objective should be commercially competitive chips, not protected products that cannot win customers outside a programme. Export wins would provide the clearest proof that public support created globally useful capability.
Repeat customers would make that commercial proof stronger, clearer and more durable.
Frequently asked questions
What is the new Semicon 2.0 target?
The government says it will target at least 200 startups and companies designing chips in India. This is an ecosystem participation target, not a guarantee that every participant will receive funding.
How large is the Semicon 2.0 outlay?
The Union Cabinet approved a total programme outlay of ₹1,27,500 crore in July 2026.
What are the six pillars?
They are chip design, machines and materials, new fabrication units, advanced packaging, applied research and development, and talent development.
How should progress be measured?
Beyond approvals and training, useful measures include completed tape-outs, working samples, customer qualifications, volume production, domestic value addition and recurring commercial revenue.
Verified sources
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